US 12,422,482 B2
Apparatuses and methods for faciliatating a dynamic clock frequency for at-speed testing
Chandan Gupta, Greater Noida (IN); Satish Chandra Tiwari, Noida (IN); and Abhishek Ashok Bajpaee, Vadodara (IN)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Nov. 1, 2023, as Appl. No. 18/499,743.
Claims priority of application No. 202341061147 (IN), filed on Sep. 12, 2023.
Prior Publication US 2025/0085344 A1, Mar. 13, 2025
Int. Cl. G01R 31/3185 (2006.01); G01R 31/317 (2006.01); G01R 31/319 (2006.01)
CPC G01R 31/318552 (2013.01) [G01R 31/31727 (2013.01); G01R 31/31922 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a processing system including a processor; and
a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations, the operations comprising:
monitoring first data of a first plurality of test points;
analyzing the first data of first plurality of test points to identify a first time domain included in a plurality of time domains, wherein respective portions of a device under test (DUT) are operative in accordance with a given time domain included in the plurality of time domains; and
based on the analyzing of the first plurality of test points, generating first control signals to cause a first clock signal to be adapted to generate a second clock signal that is different from the first clock signal, wherein the first time domain defines a portion of the device arranged to be tested at a defined time based on a frequency of the second clock signal.