US 12,422,481 B2
Semiconductor chip and sequence checking circuit
Hung-Yi Chang, Hsinchu (TW); Bi-Yang Li, Hsinchu (TW); and Shih-Cheng Kao, Hsinchu (TW)
Assigned to GLOBAL UNICHIP CORPORATION, Hsinchu (TW); and TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by GLOBAL UNICHIP CORPORATION, Hsinchu (TW); and TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Mar. 27, 2023, as Appl. No. 18/190,144.
Claims priority of application No. 111137371 (TW), filed on Sep. 30, 2022.
Prior Publication US 2024/0110978 A1, Apr. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 19/00 (2006.01); G01R 31/3185 (2006.01); H03K 3/037 (2006.01); H03K 19/21 (2006.01); H10B 80/00 (2023.01)
CPC G01R 31/318525 (2013.01) [G11C 19/00 (2013.01); H03K 3/037 (2013.01); H03K 19/21 (2013.01); H10B 80/00 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A semiconductor chip, comprising:
a physical layer, comprising an input/output circuit, at least one sequence checking circuit and at least one signal transmission path, wherein the at least one sequence checking circuit is configured to generate at least one test result signal according to a clock signal transmitted through the input/output circuit and at least one test data signal transmitted through the at least one signal transmission path; and
a processing circuit, electrically coupled to the physical layer and configured to determine an operation status of the at least one signal transmission path according to a voltage level of the at least one test result signal,
wherein the at least one sequence checking circuit comprises:
a shift register circuit, configured to check a plurality of data values of at least one test data signal according to a plurality of rising edges and a plurality of falling edges of the clock signal, so as to output a first checking result signal; and
an output terminal logic gate, configured to output the at least one test result signal according to a voltage level of the first checking result signal.