US 12,422,480 B1
Detecting hardware errors
Tom Kolan, Haifa (IL); Adi Habusha, Alonei Abba (IL); Nicolas Worms, Haifa (IL); and Ilan Wachtel, Mazkeret Batya (IL)
Assigned to Amazon Technologies, Inc., Seattle, WA (US)
Filed by Amazon Technologies, Inc., Seattle, WA (US)
Filed on Jun. 20, 2023, as Appl. No. 18/338,025.
Int. Cl. G01R 31/3183 (2006.01); G01R 31/3177 (2006.01)
CPC G01R 31/318385 (2013.01) [G01R 31/3177 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for detecting hardware errors in an integrated circuit (IC) device that includes a plurality of processing cores, comprising:
generating a plurality of test templates, wherein each test template includes a set of instructions to create scenarios for detection of the hardware errors;
periodically generating a binary image that includes a plurality of random tests corresponding to the plurality of test templates; and
for each binary image:
executing the binary image on the IC device for a first pass;
storing a result of the first pass as a golden result;
executing the binary image on the IC device in subsequent passes by changing logical roles of which processor core executes which test in each pass to have each processor core execute a test previously executed by another processor core; and
comparing results of the subsequent passes against the golden result to detect a hardware error in the IC device.