| CPC G01R 31/3177 (2013.01) | 20 Claims |
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1. An integrated-circuit chip comprising:
a plurality of processors;
a system memory;
a main system bus for carrying data between each of the plurality of processors and the system memory;
debug logic;
a debug port for communicating with the debug logic from outside the chip;
a debug connection that connects the debug logic to the main system bus; and
a power management system for controlling the power supplied to each of a plurality power domains on the chip;
wherein the debug logic and each of the plurality of processors are in different respective power domains of the plurality of power domains;
wherein the debug logic is configured to send a debug instruction to any of the plurality of processors, wherein the debug instruction is communicated over the debug connection and over the main system bus;
wherein the main system bus comprises a bus arbiter configured to prioritize bus transactions on the main system bus; and
wherein the bus arbiter is configured to prioritize a bus transaction associated with the debug instruction higher or lower than a memory read or write transaction between a processor of the plurality of processors and the system memory.
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