US 12,422,477 B2
Segmented row repair for programmable logic devices
Dheeraj Subbareddy, Portland, OR (US); Arun Jangity, Sunnyvale, CA (US); Ramya Yeluri, Mountain View, CA (US); Mahesh K. Kumashikar, Bangalore (IN); Atul Maheshwari, Portland, OR (US); and Ankireddy Nalamalpu, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2021, as Appl. No. 17/559,322.
Prior Publication US 2022/0113350 A1, Apr. 14, 2022
Int. Cl. G01R 31/3177 (2006.01); G06F 11/16 (2006.01); G06F 11/20 (2006.01)
CPC G01R 31/3177 (2013.01) [G06F 11/16 (2013.01); G06F 11/202 (2013.01); G06F 11/2043 (2013.01); G06F 11/2046 (2013.01); G06F 11/2048 (2013.01); G06F 11/2094 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A programmable logic device comprising:
a plurality of logic array blocks comprising a plurality of programmable elements, wherein the plurality of logic array blocks is arranged in a plurality of rows that are each segmented into a plurality of segments that are each smaller than a row and that are separately repairable independent of other segments in the same row; and
repair circuitry disposed between the plurality of segments that remaps logic within a first segment of the plurality of segments when a first logic array block of the plurality of logic array blocks has failed, wherein the first segment comprises the first logic array block.