US 12,422,465 B2
In-situ chip design for pulse IV self-heating evaluation
Huimei Zhou, Albany, NY (US); Yoo-Mi Lee, Montvale, NJ (US); Jingyun Zhang, Albany, NY (US); Miaomiao Wang, Albany, NY (US); and Huiming Bu, Glenmont, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 28, 2023, as Appl. No. 18/456,775.
Prior Publication US 2025/0076365 A1, Mar. 6, 2025
Int. Cl. G01R 31/26 (2020.01)
CPC G01R 31/2628 (2013.01) 23 Claims
OG exemplary drawing
 
1. An in-situ chip design for self-heating free characterization of a device under test (DUT) with a short time constant, the in-situ chip design comprising:
a transistor disposed as the DUT and comprising a drain pad, a source pad and a gate;
a pulse generator configured to output a pulse to the gate of the DUT;
a buffering circuit arranged between the pulse generator and the DUT; and
a first optional circuit with a selectable force pad and a selectable control path to the DUT, the selectable control path comprising:
a switch to which the selectable force pad is connected;
a first optional circuit pad; and
an extra buffer electrically interposed between the first optional circuit pad and the switch,
the buffering circuit comprising a first switch and an adjustable buffer circuit in parallel with the first switch and being controllable to apply one of various degrees of buffering to the pulse.