US 12,421,103 B2
Microelectromechanical system device
Chen Hsiung Yang, Hsinchu County (TW); Chun-Wen Cheng, Hsinchu County (TW); Chia-Hua Chu, Hsinchu County (TW); and En-Chan Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Feb. 12, 2023, as Appl. No. 18/167,884.
Application 17/114,403 is a division of application No. 16/116,105, filed on Aug. 29, 2018, granted, now 10,865,099, issued on Dec. 15, 2020.
Application 18/167,884 is a continuation of application No. 17/114,403, filed on Dec. 7, 2020, granted, now 11,577,954.
Prior Publication US 2023/0192476 A1, Jun. 22, 2023
Int. Cl. B81B 3/00 (2006.01); B81B 7/00 (2006.01); B81B 7/02 (2006.01); B81C 1/00 (2006.01); H04R 19/00 (2006.01); H04R 19/04 (2006.01); H04R 31/00 (2006.01)
CPC B81B 3/0051 (2013.01) [B81B 3/0064 (2013.01); B81B 3/007 (2013.01); B81B 7/0009 (2013.01); B81B 7/0061 (2013.01); B81B 7/02 (2013.01); B81C 1/00158 (2013.01); H04R 19/005 (2013.01); B81B 2201/0257 (2013.01); B81B 2203/0307 (2013.01); B81B 2203/0361 (2013.01); H04R 19/04 (2013.01); H04R 31/00 (2013.01); H04R 2201/003 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microelectromechanical system (MEMS) device comprising:
a first multi-layer structure;
a second multi-layer structure over the first multi-layer structure;
a first semiconductor layer between the first multi-layer structure and the second multi-layer structure;
a first insulating layer between the first multi-layer structure and the first semiconductor layer;
a first air gap separating the first multi-layer structure and the first semiconductor layer;
a second air gap separating the first semiconductor layer and the second multi-layer structure;
a plurality of first semiconductor pillars exposed to the first air gap, and coupled to the first semiconductor layer and the first multi-layer structure; and
a plurality of second semiconductor pillars exposed to the second air gap, and coupled to the first semiconductor layer and the second multi-layer structure,
wherein the first multi-layer structure comprises a second insulating layer, a third insulating layer over the second insulating layer, and a second semiconductor layer between the second insulating layer and the third insulating layer, and
wherein the second semiconductor layer is entirely separated from the first insulating layer.