US 12,096,623 B2
Vertical semiconductor device, manufacturing method therefor, integrated circuit and electronic device
Huilong Zhu, Poughkeepsie, NY (US); Weixing Huang, Beijing (CN); and Kunpeng Jia, Beijing (CN)
Assigned to Institute of Microelectronics, Chinese Academy of Sciences China, Beijing (CN)
Appl. No. 17/309,775
Filed by Institute of Microelectronics, Chinese Academy of Sciences, Beijing (CN)
PCT Filed Apr. 9, 2019, PCT No. PCT/CN2019/081906
§ 371(c)(1), (2) Date Jun. 17, 2021,
PCT Pub. No. WO2020/124876, PCT Pub. Date Jun. 25, 2020.
Claims priority of application No. 201811577677.6 (CN), filed on Dec. 20, 2018.
Prior Publication US 2022/0085043 A1, Mar. 17, 2022
Int. Cl. H10B 41/27 (2023.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01)
CPC H10B 41/27 (2023.02) [H01L 29/42324 (2013.01); H01L 29/788 (2013.01)] 37 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
an active region on the substrate, wherein the active region comprises a first source and drain layer, a channel layer, and a second source and drain layer sequentially stacked on the substrate;
a gate stack formed around an outer periphery of the channel layer, wherein the gate stack is self-aligned with the channel layer, and wherein the gate stack comprises a gate dielectric layer and a gate conductor layer; and
an intermediate dielectric layer and a second conductive layer around an outer periphery of the gate stack and an outer periphery of the active region,
wherein the gate conductor layer is completely insulated from the first source and drain layer and from the second source and drain layer.