US 12,096,616 B2
Semiconductor structure and manufacturing method thereof
Ming Cheng, Hefei (CN); Xing Jin, Hefei (CN); and Ran Li, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jul. 30, 2021, as Appl. No. 17/389,752.
Application 17/389,752 is a continuation of application No. PCT/CN2021/100205, filed on Jun. 15, 2021.
Claims priority of application No. 202010988655.X (CN), filed on Sep. 18, 2020.
Prior Publication US 2022/0093605 A1, Mar. 24, 2022
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/482 (2023.02) [H10B 12/315 (2023.02)] 6 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor structure, comprising:
providing a substrate, and sequentially stacking a bit line structure and a first sacrificial layer on the substrate, wherein capacitor contact holes are located on two opposite sides of the bit line structure, and the first sacrificial layer is located on the bit line structure;
forming an isolation sidewall covering a sidewall of the bit line structure and a sidewall of the first sacrificial layer; and
removing the first sacrificial layer to form a gap, wherein the gap is located on the bit line structure.