US 12,095,478 B2
Memory and operation method of memory
Jin Ho Jeong, Gyeonggi-do (KR); Dae Suk Kim, Gyeonggi-do (KR); and Munseon Jang, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jul. 29, 2022, as Appl. No. 17/877,484.
Application 17/877,484 is a continuation in part of application No. 17/330,881, filed on May 26, 2021, granted, now 11,442,810.
Claims priority of provisional application 63/094,415, filed on Oct. 21, 2020.
Claims priority of provisional application 63/042,193, filed on Jun. 22, 2020.
Prior Publication US 2022/0368351 A1, Nov. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 13/11 (2006.01); H03M 13/15 (2006.01); G06F 17/16 (2006.01); G11C 29/52 (2006.01); H03M 13/00 (2006.01); H03M 13/05 (2006.01); H03M 13/25 (2006.01); H03M 13/29 (2006.01)
CPC H03M 13/1177 (2013.01) [H03M 13/1575 (2013.01); H03M 13/159 (2013.01); G06F 17/16 (2013.01); G11C 29/52 (2013.01); H03M 13/05 (2013.01); H03M 13/116 (2013.01); H03M 13/255 (2013.01); H03M 13/2906 (2013.01); H03M 13/616 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A memory, comprising:
a first check matrix calculation circuit suitable for generating a first parity from a group indicator portion of a check matrix including stored write data, wherein the stored write data includes N data groups each of which is input through a different data pad, and the group indicator portion distinguishes the N data groups, where N is a positive integer;
a memory core suitable for storing the stored write data and the first parity;
a first syndrome calculation circuit suitable for generating a first syndrome by adding the first parity which is read from the memory core to a first calculation result obtained by calculating a product of the group indicator portion of the check matrix including the stored write data and read data which is read from the memory core; and
a failure determination circuit suitable for accumulating the first syndrome for a region of the memory core to generate a vector, determining a presence of a failure of the region based on the vector, correcting the failure to thereby correct the read data read from the memory core, and transferring the corrected read data from the memory core.