US 12,095,467 B2
Compact digital delay locked loop
Anand Meruva, San Diego, CA (US); Jeffrey Mark Hinrichs, San Diego, CA (US); and Prince Mathew, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Oct. 26, 2022, as Appl. No. 17/974,460.
Prior Publication US 2024/0146313 A1, May 2, 2024
Int. Cl. H03L 7/081 (2006.01); H03K 5/131 (2014.01); H03K 5/134 (2014.01); H03K 5/00 (2006.01)
CPC H03L 7/0814 (2013.01) [H03K 5/131 (2013.01); H03K 5/134 (2014.07); H03L 7/0818 (2013.01); H03K 2005/00058 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system, comprising:
a delay buffer, comprising:
a delay device having an input, an output, and a first current terminal;
a first current circuit coupled between a first rail and the first current terminal, wherein the first current circuit comprises:
first transistors; and
first switches, wherein each one of the first switches is coupled in series with a respective one of the first transistors between the first rail and the first current terminal; and
a voltage circuit coupled to gates of the first transistors, wherein the voltage circuit is configured to output a first control voltage to the gates of the first transistors, receive a digital code, and set a voltage level of the first control voltage based on the digital code.