	US 12,094,881 B2
	Arsenic-doped epitaxial source/drain regions for NMOS
Anand Murthy, Portland, OR (US); Ryan Keech, Portland, OR (US); Nicholas G. Minutillo, Hillsboro, OR (US); and Ritesh Jhaveri, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 10, 2023, as Appl. No. 18/108,526.
Application 18/108,526 is a division of application No. 16/145,375, filed on Sep. 28, 2018, granted, now 11,610,889.
Prior Publication US 2023/0197729 A1, Jun. 22, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/167 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)

CPC H01L 27/0924 (2013.01) [H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/167 (2013.01); H01L 29/4966 (2013.01); H01L 29/518 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01)]

17 Claims

1. An integrated circuit structure, comprising:

a bulk silicon substrate;

a gate structure over the bulk silicon substrate, the gate structure being part of an NMOS transistor device; and

a source region and a drain region to respective sides of the gate structure, the source region and the drain region each being a bi-layer structure including a first layer and a second layer, wherein the first layer includes an arsenic concentration in a range of 1E20 atoms per cm³to 5E21 atoms per cm³, and the second layer includes semiconductor fill.