US 12,094,841 B2
Distributing on chip inductors for monolithic voltage regulation
Michael Henry Soltau Dayringer, Belmont, CA (US); Anatoly Yakovlev, San Francisco, CA (US); Ji Eun Jang, Foster City, CA (US); Hesam Fathi Moghadam, Sunnyvale, CA (US); and David Hopkins, Carson City, NV (US)
Assigned to Oracle International Corporation, Redwood City, CA (US)
Filed by Oracle International Corporation, Redwood City, CA (US)
Filed on May 3, 2021, as Appl. No. 17/306,870.
Application 17/306,870 is a division of application No. 16/159,448, filed on Oct. 12, 2018, granted, now 11,024,589.
Claims priority of provisional application 62/572,334, filed on Oct. 13, 2017.
Prior Publication US 2021/0257317 A1, Aug. 19, 2021
Int. Cl. H01L 23/64 (2006.01); G05F 1/46 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H02M 1/14 (2006.01); H02M 3/158 (2006.01); H01F 27/24 (2006.01); H02M 1/00 (2006.01)
CPC H01L 23/645 (2013.01) [G05F 1/462 (2013.01); H01L 23/5227 (2013.01); H01L 24/17 (2013.01); H02M 1/14 (2013.01); H02M 3/158 (2013.01); H01F 27/24 (2013.01); H01L 2924/1206 (2013.01); H02M 1/0048 (2021.05)] 20 Claims
OG exemplary drawing
 
1. A processor, comprising:
an integrated voltage regulator comprising a plurality of pairs of inductors implemented on a die of the processor, wherein the pairs of inductors are not evenly distributed amongst different voltage domains, wherein a respective clock phase assigned to a first inductor of each of the pairs is different than a respective clock phase assigned to a second one of each of the pairs, and wherein the different voltage domains are enabled or disabled according to the respective clock phases assigned to the pairs of inductors; and
the pairs of inductors configured to regulate voltage as part of a power distribution network (PDN) for different respective portions of the die.