CPC H01L 23/36 (2013.01) [H01L 21/4871 (2013.01); H01L 21/4875 (2013.01); H01L 27/1203 (2013.01)] | 20 Claims |
1. A method, comprising:
forming an oxide layer over a top surface of a substrate;
depositing a layer of semiconductor material over the oxide layer; and
manufacturing a thermal substrate contact extending through the layer of semiconductor material and the oxide layer to the top surface of the substrate, wherein manufacturing the thermal substrate contact comprises:
etching a recess, wherein the etching exposes a top-most surface of the substrate;
filling the recess with a thermally conductive material, wherein the thermally
conductive material lands on the top-most surface of the substrate;
manufacturing a transistor having, in the layer of semiconductor material, an N-well, a P-well, and a channel; and
manufacturing an interconnect structure over the thermal substrate contact, wherein the thermal substrate contact is electrically connected to the interconnect structure,
wherein etching the recess comprises:
etching a first opening through the layer of semiconductor material to expose the oxide layer; and
etching a second opening through the first opening to expose the substrate, wherein etching the second opening is a different process from etching the first opening,
wherein filling the recess comprises:
depositing the thermally conductive material into the first opening; and
depositing the thermally conductive material into the second opening.
|