US 12,094,569 B2
3D memory structure and circuit
Chung-Kuang Chen, Hsinchu (TW); and Chun-Hsiung Hung, Hsinchu (TW)
Assigned to MACRONIX International Co., Ltd., Hsinchu (TW)
Filed by MACRONIX International Co., Ltd., Hsinchu (TW)
Filed on Mar. 14, 2022, as Appl. No. 17/694,313.
Prior Publication US 2023/0290392 A1, Sep. 14, 2023
Int. Cl. G11C 7/18 (2006.01)
CPC G11C 7/18 (2013.01) [G11C 2207/005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional memory structure, comprising:
a memory array, including a first sub-array and a second sub-array, each having a first selection line, a plurality of word lines, and a second selection line;
a connection structure, including a plurality of connection areas, and at least one of extension structures of the first selection line, the plurality of word lines, and the second selection line is coupled to a corresponding connection area of the plurality of connection areas, wherein each of the plurality of connection areas extends from the first sub-array to the second sub-array, and each of the extension structure is a non-cutting area, and the first selection line, the plurality of word lines, and the second selection line of the first sub-array are respectively coupled to the first selection line, the plurality of word lines and the second selection line of the second sub-array through each of the extension structures;
a pass gate set, arranged under the connection structure and between the first sub-array and the second sub-array, wherein the pass gate set includes a plurality of pass gates, and the plurality of pass gates are respectively coupled to the corresponding plurality of connection areas; and
a drive circuit, coupled to the pass gate set, and disposed under the connection structure.