CPC G11C 5/148 (2013.01) | 19 Claims |
1. A non-volatile memory, comprising:
a processing unit generating a standby signal;
a power supply unit connected with a first node, and receiving the standby signal, wherein when the standby signal is not asserted, a supply voltage is converted into an array voltage with a first value by the power supply unit, and the array voltage is provided to the first node, wherein when the standby signal is asserted, the power supply unit stops generating the array voltage;
a voltage detecting circuit connected with the first node, and receiving the standby signal, wherein when the standby signal is asserted, the voltage detecting circuit detects the array voltage at the first node; and
a memory module connected with the first node, and receiving the array voltage,
wherein when the array voltage decreases and reaches a second value, the voltage detecting circuit asserts an enable signal to enable the processing unit, and the processing unit deasserts the standby signal,
wherein when the array voltage increases and reaches the first value, the processing unit asserts the standby signal, and the voltage detecting circuit deasserts the enable signal.
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