US 12,094,558 B2
Multiple stack high voltage circuit for memory
Perng-Fei Yuh, Hsinchu (TW); Meng-Sheng Chang, Hsinchu (TW); Tung-Cheng Chang, Hsinchu (TW); and Yih Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 16, 2023, as Appl. No. 18/318,264.
Application 18/318,264 is a continuation of application No. 17/460,938, filed on Aug. 30, 2021, granted, now 11,682,433.
Prior Publication US 2023/0282250 A1, Sep. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G11C 5/14 (2006.01); G11C 7/10 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01)
CPC G11C 5/147 (2013.01) [G11C 7/1084 (2013.01); G11C 17/165 (2013.01); G11C 17/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory array, comprising:
a first stack pass gate comprising a first PMOS core device and a second PMOS core device connected in series;
a first stack selector comprising a first NMOS core device and a second NMOS core device connected in series; and
a first resistive element coupled between a first bit line and the first stack selector;
wherein the first stack pass gate is configured to couple a voltage supply to the first resistive element through the first bit line; and
wherein the voltage supply is greater than a breakdown voltage for each of the first PMOS core device, the second PMOS core device, the first NMOS core device, and the second NMOS core device.