US 12,094,555 B2
Stacked semiconductor device
Jae Hyung Park, Gyeonggi-do (KR); Seung Geun Baek, Gyeonggi-do (KR); and Dong Uk Lee, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Aug. 10, 2022, as Appl. No. 17/884,963.
Claims priority of application No. 10-2022-0031987 (KR), filed on Mar. 15, 2022.
Prior Publication US 2023/0298631 A1, Sep. 21, 2023
Int. Cl. G11C 5/00 (2006.01); G11C 5/02 (2006.01); G11C 8/10 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC G11C 5/02 (2013.01) [G11C 8/10 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A stacked semiconductor device comprising:
at least one upper chip including
a plurality of channels each including first and second pseudo-channels; and
a plurality of transfer control circuits respectively corresponding to the channels and each configured to output channel commands according to a channel designation signal designating one of the first and second pseudo-channels and a location information signal indicating a location of a corresponding channel of the channels, and transmit first and second data words between the corresponding channel and a lower chip according to the channel commands.