US 12,094,554 B2
Memory device, failure bits detector and failure bits detection method thereof
Chung-Han Wu, Kaohsiung (TW); Che-Wei Liang, Hsinchu County (TW); Chih-He Chiang, Hsinchu County (TW); and Shang-Chi Yang, Changhua County (TW)
Assigned to MACRONIX International Co., Ltds., Hsinchu (TW)
Filed by MACRONIX International Co., Ltd., Hsinchu (TW)
Filed on Oct. 5, 2022, as Appl. No. 17/960,149.
Prior Publication US 2024/0120018 A1, Apr. 11, 2024
Int. Cl. G11C 29/52 (2006.01); G05F 3/26 (2006.01)
CPC G11C 29/52 (2013.01) [G05F 3/262 (2013.01)] 19 Claims
OG exemplary drawing
 
10. A failure bits detection method, comprising:
generating a first current according to a reference code by a current generator, and generating a first voltage according to the first current;
providing a current mirror to mirror the first current to generate a second current and provide the second current to a page buffer to generate a second voltage; and
providing the first voltage to a first input end of a comparator, providing the second voltage to a second input end of the comparator, and generating a detection result according to a difference between the first voltage and the second voltage,
wherein the current generator comprises:
at least one first transistor having a first end coupled to the first end of the current mirror and a control end receiving the reference code; and
a second transistor coupled between a second end of the at least one first transistor and a reference ground end, and controlled by a bias voltage.