US 12,094,551 B2
Modular error correction code circuitry
Hwa Chaw Law, Kuala Langat (MY); and Yu Ying Ong, Bayan Lepas (MY)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 24, 2020, as Appl. No. 17/133,810.
Prior Publication US 2021/0151120 A1, May 20, 2021
Int. Cl. G11C 29/42 (2006.01); G11C 29/00 (2006.01); G11C 29/12 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/1201 (2013.01); G11C 29/44 (2013.01); G11C 29/78 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multi-die system, comprising:
a first die comprising a core circuit and a peripheral circuit wherein a portion of the core circuit and a portion of the peripheral circuit are reconfigurable;
a second die; and
a multi-channel link configured to provide an interconnection between the first die and the second die, comprising:
a plurality of channels configured to transmit a plurality of data bits and a plurality of parity bits, wherein a channel of the plurality of channels is a default channel, and wherein the default channel is configured to receive the plurality of parity bits from the plurality of channels; and
a plurality of Error Correction Code (ECC) modules configured to provide error handling for the plurality of channels, wherein the error handling corresponds to a parity check matrix that is reconfigurable, wherein each of the plurality of ECC modules corresponds to a respective matrix of a plurality of matrices derived from partitioning the parity check matrix, wherein each of the plurality of ECC modules coupled to a respective channel of the plurality of channels is configured to processes a portion of the plurality of data bits transmitted via the respective channel, wherein an ECC module of the plurality of ECC modules coupled to the default channel is configured to processes the plurality of parity bits.