US 12,094,549 B2
Defect detection during erase operations
Jun Xu, San Jose, CA (US); and Kitae Park, Cupertino, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 17, 2022, as Appl. No. 17/889,578.
Claims priority of provisional application 63/239,534, filed on Sep. 1, 2021.
Prior Publication US 2023/0067457 A1, Mar. 2, 2023
Int. Cl. G11C 29/12 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/34 (2006.01)
CPC G11C 29/12 (2013.01) [G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/3445 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
initiating an erase operation comprising a plurality of sub-operations performed with respect to the memory array;
determining whether an erase verify sub-operation of the plurality of sub-operations is successful;
in response to determining that the erase verify sub-operation is successful, causing a select gate scan sub-operation of the plurality of sub-operations to be performed;
during at least one sub-operation of the plurality of sub-operations, causing at least one current differential to be identified between a pair of components of the memory array;
determining whether the at least one current differential is indicative of at least one defect with respect to at least one corresponding failure point of the memory array; and
in response to determining that the at least one current differential is indicative of the at least one defect with respect to the at least one failure point, causing an indication of the at least one defect to be generated.