US 12,094,548 B1
Diagnosing faults in memory periphery circuitry
Grigor Tshagharyan, Yerevan (AM); Gurgen Harutyunyan, Yerevan (AM); and Yervant Zorian, Santa Clara, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Apr. 13, 2023, as Appl. No. 18/134,198.
Int. Cl. G11C 29/10 (2006.01); G11C 7/06 (2006.01); G11C 7/22 (2006.01)
CPC G11C 29/10 (2013.01) [G11C 7/22 (2013.01); G11C 7/06 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving, at a test device, a first test syndrome from a memory device, the first test syndrome corresponds to a first test process executed by the memory device, wherein the memory device comprises a memory array and peripheral circuitry, the peripheral circuitry comprises a first circuit element external to and coupled with the memory array and configured to perform at least a portion of a memory command associated with the memory array, and wherein the first test process is associated with the first circuit element;
determining, by a processing device of the test device, a first fault associated with the first circuit element based on the first test syndrome; and
diagnosing, by the processing device, the first fault to determine positional information of the first fault, the positional information is associated with the first circuit element.