US 12,094,547 B2
Continuous memory programming operations
Violante Moschiano, Avezzano (IT); Ali Mohammadzadeh, Mountain View, CA (US); Walter Di Francesco, Avezzano (IT); and Dheeraj Srinivasan, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 23, 2022, as Appl. No. 17/893,364.
Claims priority of provisional application 63/239,748, filed on Sep. 1, 2021.
Prior Publication US 2023/0060312 A1, Mar. 2, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 7/1039 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array comprising a plurality of memory cells electrically coupled to a plurality of conductive lines; and
a controller coupled to the memory array, the controller to perform operations comprising:
performing a memory programming operation with respect to a set of memory cells of the memory array, wherein the memory programming operation comprises a first sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells;
responsive to receiving a command to perform a memory access operation, suspending the memory programming operation after performing a current programming pulse of the sequence of programming pulses, wherein the current programming pulse is performed at a first voltage level;
initiating the memory access operation;
resuming the memory programming operation by performing a second sequence of programming pulses applied to the one or more conductive lines; and
completing the memory access operation by storing one or more data items read from the memory array in an input/output (I/O) buffer associated with the set of memory cells, wherein the I/O buffer is not utilized by the memory programming operation.