US 12,094,545 B2
Techniques for preventing read disturb in NAND memory
Arun Sitaram Athreya, Folsom, CA (US); Shankar Natarajan, Folsom, CA (US); Sriram Natarajan, Folsom, CA (US); Yihua Zhang, Folsom, CA (US); and Suresh Nagarajan, Folsom, CA (US)
Assigned to Intel NDTM US LLC, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 18, 2023, as Appl. No. 18/235,727.
Application 18/235,727 is a continuation of application No. 16/715,791, filed on Dec. 16, 2019, granted, now 11,769,557.
Prior Publication US 2023/0395166 A1, Dec. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3427 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile storage device comprising:
a NAND storage array including blocks of memory cells; and
logic to:
receive a read request to access a wordline in a first NAND memory block, each memory cell at the wordline to store two or more bits, detect that a number of reads to the wordline exceeds a threshold, and move data stored at the wordline to a single level cell (SLC) buffer.