US 12,094,542 B2
Device and method to generate bias voltages in non-volatile memory
Vikas Rana, Noida (IN); and Neha Dalal, Paschim Vihar (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Dec. 3, 2021, as Appl. No. 17/542,323.
Claims priority of provisional application 63/122,835, filed on Dec. 8, 2020.
Prior Publication US 2022/0180944 A1, Jun. 9, 2022
Int. Cl. G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/30 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/0408 (2013.01); G11C 16/08 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A non-volatile memory circuit, comprising:
a main memory array;
a plurality of sense amplifiers coupled to the main memory array;
a bias replica circuit coupled to the main memory array;
a cascode voltage generation circuit coupled to the plurality of sense amplifiers and to the bias replica circuit;
a current mirror;
a current comparator;
an oscillator coupled to the current comparator;
a phase generator coupled to the oscillator; and
a charge pump coupled to the phase generator and the bias replica circuit.