CPC G11C 16/26 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 29/52 (2013.01); G11C 16/08 (2013.01); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] | 20 Claims |
1. A controller for controlling a first nonvolatile memory including a memory cell array including a plurality of cell units each including a plurality of memory cells, the controller being configured to:
read a first data set from a first cell unit of the cell units in the first nonvolatile memory by using a first voltage and a second voltage;
read a first single state data set from the first cell unit by using a third voltage between the first voltage and the second voltage;
generate a first expected data set by an error correction on the first data set;
store, in a first buffer, the first data set, the first expected data set, and the first single state data set;
extract, from the first data set, bits corresponding to a first value of the first single state data set as a second data set;
extract, from the first expected data set, bits corresponding to the first value of the first single state data set as a second expected data set;
count a number of first memory cells corresponding to a first combination of the second data set and the second expected data set;
count a number of second memory cells corresponding to a second combination of the second data set and the second expected data set;
calculate a shift amount of the first voltage based on the counted number of the first memory cells and the counted number of the second memory cells; and
apply the shift amount to a next read operation of reading data from the first cell unit.
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