| CPC G11C 16/20 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/3427 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] | 17 Claims |
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1. A three dimensional non-volatile memory device, comprising:
a memory cell array including a cell string, the cell string including a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate, wherein the memory cells comprise a first cell group and a second cell group stacked on the first cell group, and wherein a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate;
an address decoder configured to a supply string selection line voltage to the string selection transistor, word line voltages to word lines connected to the memory cells, a ground selection line voltages to the ground selection transistor, and a common source line voltage to a common source line of the memory cell array;
a page buffer circuit configured to output bit data from selected ones of the memory cells of the memory cell array;
control logic; and
a voltage generator configured to supply voltages to the address decoder in response to the control logic,
wherein the memory device is configured to initialize a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then apply a program voltage to the memory cell of the pillar structure of the cell string,
wherein the horizontal width of the pillar structure for the first cell group of the cell string decreases in the depth direction towards the substrate and the horizontal width of the pillar structure for the second cell group of the cell string increases in the depth direction towards the substrate, and wherein the memory device is configured to:
sequentially program the memory cells of the second cell group in order from a lowermost memory cell of the second cell group closest to the substrate to an uppermost memory cell of the second cell group furthest from the substrate; and then
sequentially program the memory cells of the first cell group in order from an uppermost memory cell of the first cell group furthest from the substrate to a lowermost of the first cell group closest to the substrate.
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