US 12,094,538 B2
Architecture and method for NAND memory operation
Kaijin Huang, Wuhan (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Mar. 29, 2021, as Appl. No. 17/215,005.
Application 17/215,005 is a continuation of application No. PCT/CN2021/070811, filed on Jan. 8, 2021.
Prior Publication US 2022/0223210 A1, Jul. 14, 2022
Int. Cl. G11C 16/14 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/14 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3445 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for erasing a memory device including memory cells, comprising:
performing a first erase operation on a selected memory cell of the memory cells based on a first erase voltage;
performing a first erase verifying operation on the selected memory cell based on a first erase verify voltage; and
performing a second erase verifying operation on the selected memory cell based on a second erase verify voltage after the selected memory cell passes the first erase verifying operation, the first erase verify voltage being greater than the second erase verify voltage.