US 12,094,528 B2
Memory with double redundancy
Dhvani Sheth, San Diego, CA (US); Hochul Lee, Los Angeles, CA (US); Anil Chowdary Kota, San Diego, CA (US); and Chulmin Jung, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jun. 6, 2022, as Appl. No. 17/833,852.
Prior Publication US 2023/0395139 A1, Dec. 7, 2023
Int. Cl. G11C 29/14 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 11/418 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A memory, comprising:
a plurality of column groups, each column group in the plurality of column groups including a plurality of multiplexed columns, the plurality of column groups including a first column group, a second column group that is adjacent to the first column group, and a third column group that is adjacent to the second column group; and
a first switch matrix configured to couple a latch to one of the first column group, the second column group, and the third column group responsive to a plurality of column redundancy signals.