CPC G11C 11/418 (2013.01) [G06N 3/065 (2023.01); G11C 11/412 (2013.01); G11C 11/419 (2013.01); H03M 1/66 (2013.01)] | 16 Claims |
1. An apparatus comprising:
a memory array, in turn comprising a plurality of word lines, a plurality of bit line pairs intersecting the plurality of word lines at a plurality of cell locations, and a plurality of memory cells, coupled to the plurality of word lines and the plurality of bit line pairs, and located at the plurality of cell locations;
a plurality of word line drivers coupled to the plurality of word lines;
a dynamic voltage boost coupled to the memory array and to the word line drivers; and
a controller coupled to the plurality of word line drivers and the dynamic voltage boost, and configured to cause the dynamic voltage boost to boost the cells during a multiply accumulate operation and to boost the word lines and the cells during a storage operation.
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