US 12,094,525 B2
Multichannel memory to augment local memory
Ravi Nair, Briarcliff Manor, NY (US); Swagath Venkataramani, White Plains, NY (US); Vijayalakshmi Srinivasan, New York, NY (US); and Arvind Kumar, Chappaqua, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jul. 22, 2022, as Appl. No. 17/814,254.
Prior Publication US 2024/0029786 A1, Jan. 25, 2024
Int. Cl. G11C 11/4096 (2006.01); G11C 5/06 (2006.01); G11C 11/4093 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 5/06 (2013.01); G11C 11/4093 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system configured to augment a capacity of a plurality of main scratchpads for a plurality of respective processing cores, the memory system comprising:
a global memory device coupled to a plurality of processing elements, wherein the global memory device is positioned external to a chip on which the plurality of processing elements reside;
at least one main scratchpad coupled to at least one processing element of the plurality of processing elements and the global memory device; and
a plurality of auxiliary scratchpads coupled to the plurality of processing elements and the global memory device, wherein at least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device.