US 12,094,524 B2
Computation in-memory using 6-transistor bit cells
Avishek Biswas, Dallas, TX (US); Mahesh Madhukar Mehendale, Dallas, TX (US); and Hetul Sanghvi, Murphy, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jan. 29, 2021, as Appl. No. 17/162,694.
Claims priority of provisional application 62/967,653, filed on Jan. 30, 2020.
Prior Publication US 2021/0240441 A1, Aug. 5, 2021
Int. Cl. G11C 11/4094 (2006.01); G06G 7/16 (2006.01); G06N 3/065 (2023.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 11/4074 (2006.01); G11C 11/4097 (2006.01); G11C 11/4099 (2006.01); G11C 11/54 (2006.01)
CPC G11C 11/4094 (2013.01) [G06G 7/16 (2013.01); G06N 3/065 (2023.01); G11C 5/06 (2013.01); G11C 7/1006 (2013.01); G11C 11/4074 (2013.01); G11C 11/4097 (2013.01); G11C 11/4099 (2013.01); G11C 11/54 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A device, comprising:
a first bit cell having a first bit cell first terminal and a first bit cell second terminal;
a second bit cell having a second bit cell first terminal and a second bit cell second terminal;
a first bit line coupled to the first bit cell first terminal;
a second bit line coupled to the first bit cell second terminal;
a third bit line coupled to the second bit cell first terminal;
a fourth bit line coupled to the second bit cell second terminal; and
a multiply and average (MAV) circuit including:
a first capacitor;
a second capacitor;
a first selection circuit having a first selection input and first terminals, the first terminals coupled to the first and second bit lines, and the first selection circuit configured to, responsive to a state of the first selection input, set a state of the first capacitor and a state of the second capacitor based on a state of the first bit cell; and
a second selection circuit having a second selection input and second terminals, the second terminals coupled to the third and fourth bit lines, and the second selection circuit configured to, responsive to a state of the second selection input, set a state of the first capacitor and a state of the second capacitor based on a state of the second bit cell.