US 12,094,520 B2
Memory device layout with intersecting region between sub-wordline and sense amplifier
Harish Gadamsetty, Allen, TX (US); and John A. Winegard, McKinney, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 26, 2022, as Appl. No. 17/584,905.
Claims priority of provisional application 63/294,522, filed on Dec. 29, 2021.
Prior Publication US 2023/0206991 A1, Jun. 29, 2023
Int. Cl. G11C 11/4091 (2006.01); G11C 5/02 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 5/025 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory partition of the memory device, wherein the memory partition comprises:
a memory region comprising a memory element coupled to a wordline of the memory region;
a sense amplifier region comprising a sense amplifier coupled to the memory element to sense a data state of the memory element;
a sub-wordline region coupled to the wordline of the memory region; and
a minigap region disposed at an intersection of the sub-wordline region and the sense amplifier region, wherein the minigap region comprises:
a first plurality of transistors having a continuous layout in at least one direction across the minigap region with a second plurality of transistors of the sense amplifier region.