CPC G11C 11/4085 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4087 (2013.01)] | 14 Claims |
1. A memory device, comprising:
a plurality of word line decoding circuit areas, arranged in an array, and forming a plurality of isolation areas, wherein each of the isolation areas is disposed between two adjacent word line decoding circuit areas;
a plurality of common power rails, wherein each of the common power rails is disposed along a plurality of the isolation areas; and
a plurality of power drivers, respectively corresponding to the word line decoding circuit areas, each of the power drivers being disposed between each of the power driving circuit areas and each of the corresponding isolation areas, wherein each of the power drivers is coupled to each of the corresponding common power rails, and is configured to provide a common power to the word line decoding circuit areas.
|