US 12,094,509 B2
Memory device which generates improved read current according to size of memory cell
Daeshik Kim, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 31, 2022, as Appl. No. 17/709,784.
Claims priority of application No. 10-2021-0045436 (KR), filed on Apr. 7, 2021.
Prior Publication US 2022/0328085 A1, Oct. 13, 2022
Int. Cl. G11C 11/16 (2006.01); G11C 17/16 (2006.01)
CPC G11C 11/1673 (2013.01) [G11C 11/161 (2013.01); G11C 11/1653 (2013.01); G11C 11/1675 (2013.01); G11C 11/1677 (2013.01); G11C 17/16 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array including a first region and a second region, the memory cell array configured to store a value of a first read current determined based on a value of a reference resistance to distinguish a parallel state and an anti-parallel state of a programmed memory cell;
a sensing circuit configured to generate the first read current based on the value of the first read current and to perform a read operation on the first region based on the first read current;
a write driver configured to perform a program operation on the first region based on a write code value,
wherein the write driver includes,
first-type transistors each including a first end connected to a first power supply voltage and a second end connected to an output node; and
second-type transistors each including a first end connected to a second power supply voltage and a second end connected to the output node.