CPC G09G 3/3266 (2013.01) [G09G 3/2074 (2013.01); G09G 3/32 (2013.01); G09G 3/3233 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0267 (2013.01)] | 20 Claims |
1. A display panel, comprising a function add-on region and a main display region surrounding the function add-on region, wherein the function add-on region comprises a light transmission display region and a transition display region located on an outer periphery of the light transmission display region, and the display panel comprises:
a plurality of pixel rows, wherein the pixel rows comprise a plurality of complex pixel rows, each of the complex pixel rows comprises a plurality of auxiliary sub-pixels located in the function add-on region and a plurality of main sub-pixels located in the main display region;
a plurality of auxiliary pixel driver circuits, wherein each of the auxiliary pixel driver circuits is connected to the auxiliary sub-pixels and is configured to drive corresponding ones of the auxiliary sub-pixels to emit light, and the auxiliary pixel driver circuits are located in the transition display region;
a plurality of main pixel driver circuits, wherein each of the main pixel driver circuits is connected to a corresponding one of the main sub-pixels to drive the corresponding one of the main sub-pixels to emit light, and the main pixel driver circuits are located in the main display region; and
gate electrode driver circuits in levels connected to the auxiliary pixel driver circuits and the main pixel driver circuits respectively through a plurality of scan signal lines, wherein the scan signal lines of each level comprises main scan signal lines of a number P and auxiliary scan signal lines of a number Q, the auxiliary scan signal lines of the number Q comprise first auxiliary scan signal lines of a number Z and second auxiliary scan signal lines of a number (Q−Z), each of the main pixel driver circuits is connected to a corresponding one of the gate electrode driver circuits through a corresponding one of the main scan signal lines, each of the auxiliary pixel driver circuits is connected to a corresponding one of the main scan signal lines through the first auxiliary scan signal line to be connected to a corresponding one of the gate electrode driver circuits, an end of each of the second auxiliary scan signal lines is connected to a corresponding one of the main scan signal lines, and another end floats; wherein P≥Q, P≥2, Q≥1, Q≥Z, Z=1, and P and Q are integers.
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