US 12,094,402 B2
Display driving device
Hiroyoshi Ichikura, Yokohama (JP)
Assigned to LAPIS SEMICONDUCTOR CO., LTD., Yokohama (JP)
Appl. No. 17/442,211
Filed by LAPIS Semiconductor Co., Ltd., Yokohama (JP)
PCT Filed Mar. 30, 2020, PCT No. PCT/JP2020/014570
§ 371(c)(1), (2) Date Sep. 23, 2021,
PCT Pub. No. WO2020/203974, PCT Pub. Date Oct. 8, 2020.
Claims priority of application No. 2019-066090 (JP), filed on Mar. 29, 2019.
Prior Publication US 2022/0172675 A1, Jun. 2, 2022
Int. Cl. G09G 3/3208 (2016.01)
CPC G09G 3/3208 (2013.01) [G09G 2330/021 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A display driving device for driving a display panel, comprising:
a high voltage operating unit that includes an output circuit to supply a driving voltage to the display panel, the high voltage operating unit being coupled to a first voltage application line to which a high power supply voltage is applied, the high voltage operating unit obtaining an operating current according to the application of the high power supply voltage from the first voltage application line;
a low voltage operating unit that operates according to an application of a low power supply voltage lower than the high power supply voltage to control the high voltage operating unit;
a recycling circuit that receives the operating current from the high voltage operating unit via a relay coupling line, the recycling circuit applying the low power supply voltage to the low voltage operating unit while supplying the received operating current to a reference potential line via the low voltage operating unit; and
a current bypass circuit that flows a part of the operating current flowing from the high voltage operation unit through the relay coupling line into the reference potential line without supplying the part of the operating current to the recycling circuit according to a voltage increase in the low power supply voltage applied to the low voltage operating unit, wherein
the current bypass circuit is configured of a clamp circuit that includes:
a field effect transistor having a gate that receives a voltage applied to the low voltage operating unit as the low power supply voltage;
a resistor having one end coupled to a drain of the field effect transistor; and
a bypass capacitor having one end coupled to the relay coupling line together with a source of the field effect transistor, the bypass capacitor having another end coupled to the reference potential line together with another end of the resistor.