CPC G09G 3/32 (2013.01) [G09G 3/3266 (2013.01); G09G 3/20 (2013.01); G09G 3/325 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01); G09G 2340/0435 (2013.01); G11C 19/28 (2013.01)] | 20 Claims |
1. A display panel, comprising:
a driving circuit comprising N stages of cascaded shift registers, wherein N≥ 2, and the shift register is configured to comprises: a first control part and a second control part,
at least receive a frequency control signal to generate an output signal,
wherein a display region of the display panel comprises a first region and a second region, and the frequency control signal comprises a first frequency control signal and a second frequency control signal; one shift register of the N stages of cascaded shift registers connected to a display unit in the first region is configured to receive the first frequency control signal; and one shift register of the N stages of cascaded shift registers connected to a display unit in the second region is configured to receive the second frequency control signal, and
wherein a data refresh frequency of the display unit in the first region is a first frequency F1, and a data refresh frequency of the display unit in the second region is a second frequency F2, wherein F1<F2;
the first frequency control signal and the second frequency control signal are signals of different potentials during at least part of a preset time period during which the display panel is operating; and a time length of the preset time period is T0, wherein T0>1/F2, or T0<1/F1.
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