US 12,094,399 B2
Power supply circuit, driving chip and display apparatus
Yingjie Ma, Beijing (CN)
Assigned to CHIPONE TECHNOLOGY (BEIJING) CO., LTD., Beijing (CN)
Appl. No. 18/255,381
Filed by CHIPONE TECHNOLOGY (BEIJING) CO., LTD., Beijing (CN)
PCT Filed Nov. 15, 2021, PCT No. PCT/CN2021/130736
§ 371(c)(1), (2) Date Jun. 1, 2023,
PCT Pub. No. WO2022/127468, PCT Pub. Date Jun. 23, 2022.
Claims priority of application No. 202011499656.4 (CN), filed on Dec. 17, 2020.
Prior Publication US 2023/0402000 A1, Dec. 14, 2023
Int. Cl. G09G 3/32 (2016.01)
CPC G09G 3/32 (2013.01) [G09G 2330/021 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A power supply circuit, wherein the power supply circuit comprises:
a reference-current generating circuit, configured to generate a reference current;
a driver circuit, connected to the reference-current generating circuit, configured to generate a mirror current with an adjustable mirror ratio according to the reference current and output a bias voltage and a gate drive voltage; and
a channel-current output circuit, connected to the driver circuit and configured to receive the bias voltage and the gate drive voltage, and generate a channel current with an adjustable mirror ratio according to the mirror current,
wherein the reference-current generating circuit comprises:
a first amplifier, comprising a inverting input terminal configured to input a reference voltage;
a resistor, comprising a first terminal grounded and a second terminal connected to a non-inverting input terminal of the first amplifier;
multi-group first P-type field-effect transistors, comprising sources connected to a power supply, gates respectively connected to a output terminal of the first amplifier, and drains connected to the second terminal of the resistor, and outputting the reference current to the resistor; and
a first switch, connected to the multi-group first P-type field-effect transistors and configured to independently control whether each group of first P-type field-effect transistors are turned on or not,
wherein the driver circuit comprises:
a second P-type field-effect transistor, comprising a source connected to the power supply, a gate connected to the gates of the multi-group first P-type field-effect transistors, and a drain configured to output the mirror current;
a second amplifier, comprising an inverting input terminal configured to input a reference voltage, and an output terminal configured to provide the gate drive voltage; and
a first N-type field-effect transistor, comprising a gate connected to the output terminal of the second amplifier, a source grounded, and a drain connected to the drain of the second P-type field-effect transistor and a non-inverting input terminal of the second amplifier, and configured to provide the bias voltage same as the reference voltage.