| CPC G09G 3/2096 (2013.01) [G09G 2310/0275 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/08 (2013.01); G11C 19/28 (2013.01)] | 24 Claims |
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1. A gate driver comprising:
a carry signal generating circuit configured to receive a vertical start signal and output a first carry signal and a second carry signal; and
a shift register circuit configured to receive the first carry signal and the second carry signal and output a first stage first carry signal, a first stage second carry signal and a first stage gate output signal,
wherein the carry signal generating circuit comprises a first carry generator configured to generate the first carry signal and a second carry generator configured to generate the second carry signal,
wherein the shift register circuit comprises a first stage first carry generator configured to generate the first stage first carry signal, a first stage second carry generator configured to generate the first stage second carry signal and a first stage output buffer configured to output the first stage gate output signal, and
wherein the second carry generator comprises:
a seventh transistor including a control electrode connected to a third node, an input electrode configured to receive a second clock signal and an output electrode connected to a second carry output terminal,
an eleventh transistor including a control electrode configured to receive a low power voltage, an input electrode connected to a first node and an output electrode connected to the third node, and
a second capacitor including a first end connected to the third node and a second end connected to the second carry output terminal.
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