US 12,094,391 B2
Display panel and display device having cascaded shift registers
Qingjun Lai, Xiamen (CN); Yihua Zhu, Xiamen (CN); and Yong Yuan, Xiamen (CN)
Assigned to Xiamen Tianma Micro-Electronics Co., Ltd., Xiamen (CN)
Filed by Xiamen Tianma Micro-Electronics Co., Ltd., Xiamen (CN)
Filed on Jun. 30, 2023, as Appl. No. 18/344,894.
Application 18/344,894 is a continuation of application No. 17/528,165, filed on Nov. 16, 2021.
Claims priority of application No. 202110519069.5 (CN), filed on May 12, 2021.
Prior Publication US 2023/0343271 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/20 (2006.01); G09G 3/3266 (2016.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/2092 (2013.01) [G09G 3/20 (2013.01); G09G 3/3266 (2013.01); G09G 3/3674 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G11C 19/28 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a driver circuit comprising N stages of cascaded shift registers, wherein N≥ 2, and a shift register of the cascaded shift registers comprises: a first control part and a second control part;
wherein the first control part is configured to receive at least a first voltage signal and a second voltage signal and control a signal of a second node and a signal of a third node, wherein one of the second node or the third node is a preset node, and another one of the second node or the third node is a non-preset node; and the second control part comprises a first control unit and a second control unit;
the first control unit is configured to receive at least a signal of the preset node and a first output control signal and control a signal of a fourth node;
the second control unit is configured to receive at least a third voltage signal and a signal of a fourth node and generate an output signal, or the second control unit is configured to receive at least a fourth voltage signal and a signal of a fifth node and generate an output signal, wherein the fifth node is connected to the non-preset node;
the first voltage signal is a low level signal, and the second voltage signal is a high level signal;
the third voltage signal is a low level signal, and the fourth voltage signal is a high level signal; and
during at least part of a time period during which the signal of the fourth node is a low level signal, each of a signal of the preset node and the first output control signal is a low level signal; and
wherein a first output control signal received by a shift register at an M1-th stage is a signal of a preset node of a shifter register at an M2-th stage, wherein 1≤M1≤N, 1≤M2≤N, 1≤|M1-M2|≤i, and 2≤i≤N-1.