US 12,094,388 B2
Source driving circuit, source driving method, display device and display driving method
Yinlong Zhang, Beijing (CN); Yanping Liao, Beijing (CN); Jiantao Liu, Beijing (CN); and Guohuo Su, Beijing (CN)
Assigned to BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/920,935
Filed by BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Oct. 22, 2021, PCT No. PCT/CN2021/125843
§ 371(c)(1), (2) Date Oct. 24, 2022,
PCT Pub. No. WO2023/065338, PCT Pub. Date Apr. 27, 2023.
Prior Publication US 2024/0221586 A1, Jul. 4, 2024
Int. Cl. G09G 3/20 (2006.01)
CPC G09G 3/2092 (2013.01) [G09G 2300/0814 (2013.01); G09G 2300/0828 (2013.01); G09G 2300/0857 (2013.01); G09G 2310/0251 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A source driving circuit, comprising:
a logic and control sub-circuit coupled to a source data signal terminal, a gate start signal terminal, a mode switching signal terminal, an initial latch enable signal terminal and a source output enable signal terminal, the logic and control sub-circuit being configured to: receive a source data signal from the source data signal terminal and convert the source data signal into a data signal; and output a first latch signal, a second latch signal, a first enable signal and a second enable signal according to a gate start signal from the gate start signal terminal, a first mode switching signal from the mode switching signal terminal, an initial latch enable signal from the initial latch enable signal terminal and a source output enable signal from the source output enable signal terminal;
a latch sub-circuit coupled to the logic and control sub-circuit, the latch sub-circuit being configured to: receive the data signal from the logic and control sub-circuit; latch an odd-numbered row of data in the data signal in an odd-numbered frame under control of the first latch signal; and latch an even-numbered row of data in the data signal in an even-numbered frame under control of the second latch signal; and
an output sub-circuit coupled to the latch sub-circuit and the logic and control sub-circuit, the output sub-circuit being configured to: receive the odd-numbered row of data in the odd-numbered frame, and output the odd-numbered row of data in a first set duration under control of the first enable signal, the first set duration being greater than a charging time of sub-pixels in the even-numbered row of a display device to which the source driving circuit applies, and being less than or equal to twice the charging time of the sub-pixels in the even-numbered row; and receive the even-numbered row of data in the even-numbered frame, and output the even-numbered row of data in a second set duration under control of the second enable signal, the second set duration being greater than a charging time of sub-pixels in the odd-numbered row of the display device, and being less than or equal to twice the charging time of the sub-pixels in the odd-numbered row.