CPC G09G 3/20 (2013.01) [G09F 9/301 (2013.01); G09G 2300/0426 (2013.01); G09G 2330/028 (2013.01); H01L 27/1218 (2013.01); H01L 27/124 (2013.01)] | 20 Claims |
1. A display panel, having a display region and a frame region outside the display region wherein the display region includes a plurality of pixel circuits, the display panel comprising:
a base substrate;
a buffer layer on a side of the base substrate, wherein the buffer layer includes an a-Si layer;
a semiconductor layer on a side of the buffer layer away from the base substrate;
a power signal layer on a side of the semiconductor layer away from the base substrate, wherein the power signal layer includes a plurality of first power voltage lines in the display region, and one first power voltage line of the plurality of first power voltage lines are electrically connected to a corresponding pixel circuit of the plurality of pixel circuits; and
an auxiliary circuit layer arranged on a side of the a-Si layer away from the power signal layer and including a plurality of auxiliary electrode lines overlapping the plurality of first power voltage lines along a direction perpendicular to a plane of the display panel, to allow an electric field to be generated in an overlapped region of the auxiliary electrode lines and the first power voltage lines.
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