US 12,094,048 B2
Multi-tile graphics processor rendering
Prasoonkumar Surti, Folsom, CA (US); Arthur Hunter, Cameron Park, CA (US); Kamal Sinha, Rancho Cordova, CA (US); Scott Janus, Loomis, CA (US); Brent Insko, Portland, OR (US); Vasanth Ranganathan, El Dorado Hills, CA (US); and Lakshminarayanan Striramassarma, Folsom, CA (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 8, 2021, as Appl. No. 17/497,618.
Application 17/497,618 is a continuation of application No. 16/355,364, filed on Mar. 15, 2019, granted, now 11,145,105.
Prior Publication US 2022/0058852 A1, Feb. 24, 2022
Int. Cl. G06T 15/00 (2011.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06T 17/20 (2006.01)
CPC G06T 15/005 (2013.01) [G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 17/20 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory for storage of data, the data including geometric data for graphics processing; and
one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tile chiplets on a substrate, each of the plurality of GPU tile chiplets being a separate semiconductor chiplet;
wherein the apparatus is to:
assign geometric data to a plurality of screen tiles for rendering of graphics;
map each of the plurality of GPU tile chiplets to a respective screen tile of the plurality of screen tiles; and
perform tile-based rendering utilizing the plurality of GPU tile chiplets, wherein the tile-based rendering includes each GPU tile chiplet to render graphics utilizing the geometric data that is assigned to the screen tile that is mapped to the GPU tile chiplet.