US 12,094,002 B2
Systems and methods for coordinating processing of instructions across multiple components
Zachary Bonig, Skokie, IL (US); Eric Thill, Naperville, IL (US); Pearce Peck-Walden, Chicago, IL (US); José Antonio Acuña-Rohter, Des Plaines, IL (US); Barry Galster, Chicago, IL (US); Neil Steuber, Evanston, IL (US); James Bailey, Hanover Park, IL (US); and Jake Siddall, Chicago, IL (US)
Assigned to Chicago Mercantile Exchange Inc., Chicago, IL (US)
Filed by Chicago Mercantile Exchange Inc., Chicago, IL (US)
Filed on May 8, 2023, as Appl. No. 18/144,677.
Application 18/144,677 is a continuation of application No. 17/169,678, filed on Feb. 8, 2021, granted, now 11,688,007.
Application 17/169,678 is a continuation of application No. 15/232,224, filed on Aug. 9, 2016, granted, now 10,943,297, issued on Mar. 9, 2021.
Prior Publication US 2023/0274356 A1, Aug. 31, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06Q 40/00 (2023.01); G06F 9/30 (2018.01); G06Q 20/00 (2012.01); G06Q 20/10 (2012.01); G06Q 40/04 (2012.01); G06Q 40/06 (2012.01)
CPC G06Q 40/04 (2013.01) [G06F 9/30043 (2013.01); G06Q 20/00 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A computer implemented method comprising:
receiving a designated computer executable instruction and a first instruction identifier corresponding to the designated computer executable instruction from a source at a same or at different times by first and second processors, located at a same or at different locations, each operative to execute designated computer executable instructions only upon subsequent separate receipt of a corresponding instruction identifier, the received designated computer executable instruction being stored in association with the first instruction identifier by each of the first and second processors in a respective instruction memory coupled therewith;
receiving, by each of the first and second processors from another source at a same or at different times subsequent to the receipt of the designated computer executable instruction and first instruction identifier, a second instruction identifier which corresponds to the first instruction identifier;
upon receiving the second instruction identifier from the other source, retrieving from the respective instruction memory by each of the first and second processors, the designated computer executable instruction associated with the first instruction identifier which corresponds to the received second instruction identifier; and
executing, by each of the first and second processors, the retrieved designated computer executable instruction; and
wherein the execution of the retrieved designated computer executable instruction by both the first and second processors is coordinated with respect to the receipt of the second instruction identifier even when the second instruction identifier is not received by the first and second processors at the same time.