CPC G06N 3/065 (2023.01) [G06F 17/16 (2013.01); G06N 3/08 (2013.01); G11C 11/15 (2013.01); H03M 1/1205 (2013.01); H03M 1/662 (2013.01)] | 19 Claims |
1. An apparatus, comprising:
a control circuit configured to connect to an array including a plurality of magnetoresistive random access memory (MRAM) memory cells connected along one or more bit lines, the control circuit is configured to:
selectively bias individual ones of the MRAM memory cells to be programmed in response to an applied external magnetic field having a field strength above a first level and below a second level; and
concurrently sense a first plurality of the MRAM memory cells connected along a shared bit line in response to a corresponding first plurality of input voltages applied to the first plurality of the MRAM memory cells,
the control circuit comprising an analog to digital converter configured to receive a value of a current in the shared bit line in response to the corresponding first plurality of input voltages applied to the first plurality of the MRAM memory cells and determine a multi-bit output value from the current.
|