US 12,093,807 B2
Neural network, method of control of neural network, and processor of neural network
Takao Marukame, Tokyo (JP); Kazuo Ishikawa, Kawasaki (JP); Junichi Sugino, Kawasaki (JP); Toshimitsu Kitamura, Kawasaki (JP); Yutaka Tamura, Kawasaki (JP); and Koji Takahashi, Kawasaki (JP)
Assigned to Kabushikiki Kaisha Toshiba, Tokyo (JP); and Toshiba Information Systems (Japan) Corporation, Kawasaki (JP)
Filed by KABUSHIKI KAISHA TOSHIBA, Tokyo (JP); and Toshiba Information Systems (Japan) Corporation, Kawasaki (JP)
Filed on Jun. 3, 2020, as Appl. No. 16/891,079.
Claims priority of application No. 2019-103803 (JP), filed on Jun. 3, 2019.
Prior Publication US 2020/0380347 A1, Dec. 3, 2020
Int. Cl. G06N 3/063 (2023.01); G06F 7/544 (2006.01)
CPC G06N 3/063 (2013.01) [G06F 7/5443 (2013.01)] 10 Claims
OG exemplary drawing
 
9. A processor of a neural network,
the neural network comprising:
at least one neuron core having a data input terminal for receiving analog input data, a data output terminal for outputting analog output data, and a weight value input terminal, the neuron core being configured to perform an analog multiply-accumulate operation based on the analog input data arriving from the data input terminal and a weight value arriving from the weight value input terminal, the weight value being analog data;
a weight-value-supply control unit connected to the weight value input terminal and supplying the weight value from the weight value input terminal to said neuron core; and
a data-hold-supply control unit connected to the data input terminal and the data output terminal, and provided with at least one second register and a second selector, the second register being configured to hold at least the analog output data operated by the neuron core and output from the data output terminal such that the hold data is suppliable to output to the second selector, and the second selector being capable of selecting any one of the at least one second register or an input data arriving from a prior stage, and wherein the second selector causes opening and closing a path for transmitting the held data in the second register to the data input termina,
wherein, the processor is configured to:
control the supply of the weight value from said weight-value-supply control unit;
process the analog output data output from the data output terminal at every analog multiply-accumulate operation performed by said neuron core as serial data and/or parallel data;
receive and hold, at the at least one second register of the data-hold-supply control unit, the analog output data output from the data output terminal; and
supply the analog output data held by the at least one second register of the data-hold-supply control unit to the data input terminal of the neuron core having the data output terminal for use in the subsequent analog multiply-accumulate operation by the neuron core,
wherein the processor is further configured to control timing of holding data at the second register of said data-hold-supply control unit and timing of opening and closing at the path, and controlling the selecting operation of the second selector with respect to the input data from the prior stage and the hold data in the second registers.