US 12,093,800 B2
Hybrid convolution operation
Eric Wayne Mahurin, Austin, TX (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 2, 2021, as Appl. No. 17/165,648.
Claims priority of provisional application 62/969,594, filed on Feb. 3, 2020.
Prior Publication US 2021/0241070 A1, Aug. 5, 2021
Int. Cl. G06N 3/04 (2023.01); G06N 3/0464 (2023.01)
CPC G06N 3/04 (2013.01) [G06N 3/0464 (2023.01)] 30 Claims
OG exemplary drawing
 
1. A device comprising:
a memory configured to store:
data corresponding to an array of input values arranged along at least a first dimension and a second dimension, and
output data corresponding to an array of output values arranged along at least the first dimension and the second dimension; and
one or more processors configured to:
retrieve a first block of the data and at least a portion of a second block of the data from the memory;
perform a first hybrid convolution operation configured to apply a filter across the first block and at least the portion of the second block to generate a first accumulated block and at least a portion of a second accumulated block; and
store the first accumulated block as first output data, wherein:
the portion of the second block is adjacent to the first block along the first dimension of the array of input values, and
the portion of the second accumulated block is adjacent to the first accumulated block along the second dimension of the array of output values.