US 12,093,748 B2
Disaggregated computing for distributed confidential computing environment
Reshma Lal, Portland, OR (US); Pradeep Pappachan, Tualatin, OR (US); Luis Kida, Beaverton, OR (US); Soham Jayesh Desai, Hillsboro, OR (US); Sujoy Sen, Beaverton, OR (US); Selvakumar Panneer, Portland, OR (US); and Robert Sharp, Austin, TX (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2020, as Appl. No. 17/133,066.
Claims priority of provisional application 63/083,565, filed on Sep. 25, 2020.
Prior Publication US 2021/0117246 A1, Apr. 22, 2021
Int. Cl. G06F 9/50 (2006.01); G06F 9/38 (2018.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01)
CPC G06F 9/5083 (2013.01) [G06F 9/3814 (2013.01); G06F 9/5027 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a host memory;
a hardware accelerator; and
one or more processors communicably coupled to the host memory and the hardware accelerator, the one or more processors to facilitate:
receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to at least one command buffer and to associated data structures and kernels of the at least one command buffer used to initialize the hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes;
identifying, based on the manifest, the at least one command buffer and the associated data structures to copy to the host memory;
identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and
patching addresses in the at least one command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.