US 12,093,736 B2
Pipeline computing apparatus, programmable logic controller, and pipeline processing execution method
Koji Nishigaki, Kusatsu (JP); Takaya Shimizu, Kyoto (JP); and Takenori Kusaka, Kyoto (JP)
Assigned to OMRON Corporation, Kyoto (JP)
Appl. No. 17/439,821
Filed by OMRON Corporation, Kyoto (JP)
PCT Filed Mar. 9, 2020, PCT No. PCT/JP2020/009930
§ 371(c)(1), (2) Date Sep. 16, 2021,
PCT Pub. No. WO2020/189360, PCT Pub. Date Sep. 24, 2020.
Claims priority of application No. 2019-053468 (JP), filed on Mar. 20, 2019.
Prior Publication US 2022/0179708 A1, Jun. 9, 2022
Int. Cl. G06F 9/50 (2006.01)
CPC G06F 9/5027 (2013.01) [G06F 9/50 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A pipeline computing apparatus, comprising:
a computing circuit comprising a plurality of nodes and a plurality of reception queues, and the computing circuit being composed of at least one of pipelines in which a plurality of the nodes are connected via the reception queues; and
a control circuit comprising a node monitoring circuit, a queue monitoring circuit, a priority variable calculating circuit, and a time allocating circuit,
wherein the node monitoring circuit acquires a node processing time, which is a time required to process one message in the node, from the node,
the queue monitoring circuit acquires an accumulated message amount of the reception queue from the reception queue,
the priority variable calculating circuit calculates a priority variable of the node based on at least the node processing time of the node and the accumulated message amount of the reception queue in a stage previous to the node, and
the time allocating circuit allocates an operating time to each node according to the priority variable for each node.